1. Technical Field
The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
2. Related Art
In recent years, development has progressed for power semiconductor modules (referred to simply as “semiconductor modules”) in which are mounted next-generation semiconductor elements such as compound semiconductor elements including silicon carbide (SiC) compound semiconductor elements and the like. An SiC element has a high withstand voltage compared to a conventional silicon (Si) semiconductor element due to having high insulation breakdown electric field strength, and it is possible to realize a miniature semiconductor module that is capable of high speed operation and has high efficiency because it is possible to make the impurity concentration higher and the active layer thinner.
The semiconductor module can use a busbar such as disclosed in Patent Document 1 or uses wiring such as disclosed in Patent Document 2, for example, to connect a plurality of modules in parallel, thereby realizing high capacitance, i.e. a large current.    Patent Document 1: Japanese Patent Application Publication No. 2014-236150    Patent Document 2: Japanese Patent Application Publication No. 2003-142689
However, miniaturization of next-generation semiconductor elements is progressing and the inductance of conductors connecting semiconductor modules in parallel, such as a busbar or wiring, is getting larger compared to the internal inductance of the semiconductor modules. Accordingly, due to variations in the inductances of the busbars, wiring, and the like for each semiconductor module, a current imbalance occurs, such as variation in the transient characteristics of the current output from each semiconductor module, e.g. the rising time, the maximum current, and the like. Until recently, it was possible to cause a busbar to have a low inductance by positioning two output lines of a semiconductor module (the P line and the N line described further below) close to each other, i.e. by using mutual inductance. However, in such a case as well, the same current imbalance occurs due to the variation in inductance from the common terminal of the busbar to each module and the semiconductor element inside each module, caused by the differences in the current paths for each semiconductor module. Since a next-generation semiconductor element operates at high speed, there is a problem that the current imbalance causes an imbalance among the switching speeds of the semiconductor modules and stress is focused on the semiconductor element in a prescribed module, thereby lowering the reliability of all of the modules.